/*
 * (C) Copyright 2017-2018 NXP
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __ARCH_ARM_MACH_S32G1_SIUL_H__
#define __ARCH_ARM_MACH_S32G1_SIUL_H__

/* SIUL2_MSCR specifications as stated in Reference Manual: */

#define SIUL2_MSCR_BASE			(SIUL2_BASE_ADDR + 0x00000240)
#define SIUL2_MSCRn(i)			(SIUL2_MSCR_BASE + 4 * (i))
#define SIUL2_IMCR_BASE			(SIUL2_BASE_ADDR + 0x00000A40)
#define SIUL2_IMCRn(i)			(SIUL2_IMCR_BASE +  4 * (i))

#define SIUL2_MSCR_MUX_MODE(v)		((v) & 0x0000000f)
#define SIUL2_MSCR_MUX_MODE_ALT0	(0x0)
#define SIUL2_MSCR_MUX_MODE_ALT1	(0x1)
#define SIUL2_MSCR_MUX_MODE_ALT2	(0x2)
#define SIUL2_MSCR_MUX_MODE_ALT3	(0x3)
#define SIUL2_MSCR_MUX_MODE_ALT4	(0x4)

/* S32-GEN1 SIUL2_MSCR masks */
#define SIUL2_MSCR_S32_G1_OBE(v)		((v) & 0x00200000)
#define SIUL2_MSCR_S32_G1_OBE_EN		(1 << 21)

#define SIUL2_MSCR_S32_G1_ODE(v)		((v) & 0x00100000)
#define SIUL2_MSCR_S32_G1_ODE_EN		(1 << 20)

#define SIUL2_MSCR_S32_G1_IBE(v)		((v) & 0x00080000)
#define SIUL2_MSCR_S32_G1_IBE_EN		(1 << 19)

#define SIUL2_MSCR_S32_G1_INV(v)		((v) & 0x00020000)
#define SIUL2_MSCR_S32_G1_INV_EN		(1 << 17)

#define SIUL2_MSCR_S32_G1_SRC(v)		((v) & 0x0001C000)
#define SIUL2_MSCR_S32_G1_SRC_208MHz		(0 << 14)
#define SIUL2_MSCR_S32_G1_SRC_150MHz		(4 << 14)
#define SIUL2_MSCR_S32_G1_SRC_100MHz		(5 << 14)
#define SIUL2_MSCR_S32_G1_SRC_50MHz		(6 << 14)
#define SIUL2_MSCR_S32_G1_SRC_25MHz		(7 << 14)

#define SIUL2_MSCR_S32_G1_PUE(v)		((v) & 0x00002000)
#define SIUL2_MSCR_S32_G1_PUE_EN		(1 << 13)

#define SIUL2_MSCR_S32_G1_PUS(v)		((v) & 0x00001000)
#define SIUL2_MSCR_S32_G1_PUS_EN		(1 << 12)

#define SIUL2_MSCR_S32_G1_RCVR(v)		((v) & 0x00000400)
#define SIUL2_MSCR_S32_G1_RCVR_DBL		(0 << 10)
#define SIUL2_MSCR_S32_G1_RCVR_SNGL		(1 << 10)

#define SIUL2_MSCR_S32_G1_SMC(v)		((v) & 0x00000020)
#define SIUL2_MSCR_S32_G1_SMC_DIS		(1 << 5)

/* S32-GEN1 UART settings */
/* TXD */
#define SIUL2_PC09_MSCR_S32_G1_UART0	41
/* RXD */
#define SIUL2_PC10_MSCR_S32_G1_UART0	42
#define SIUL2_PC10_ISCR_S32_G1_UART0	0
/* S32G2XX */
/* TXD */
#define SIUL2_PK15_MSCR_S32_G1_UART0	175
/* RXD */
#define SIUL2_PL0_MSCR_S32_G1_UART0	176
#define SIUL2_PL0_ISCR_S32_G1_UART0	0

/* UART MSCR settings */
#define SIUL2_MSCR_S32_G1_PORT_CTRL_UART_TXD	 \
	(SIUL2_MSCR_S32_G1_SRC_100MHz |		 \
	 SIUL2_MSCR_S32_G1_OBE_EN |		 \
	 SIUL2_MSCR_MUX_MODE_ALT1)

#define SIUL2_MSCR_S32_G1_PORT_CTRL_UART_RXD	 \
	(SIUL2_MSCR_S32_G1_SRC_100MHz |		 \
	 SIUL2_MSCR_S32_G1_IBE_EN |		 \
	 SIUL2_MSCR_MUX_MODE_ALT2)

/* UART IMCR mux modes */
#define SIUL2_IMCR_S32_G1_UART_RXD_to_pad	(SIUL2_MSCR_MUX_MODE_ALT2)
/* S32G2XX */
#define SIUL2_MSCR_S32G_G1_PORT_CTRL_UART_TXD	 \
	(SIUL2_MSCR_S32_G1_SRC_100MHz |		 \
	 SIUL2_MSCR_S32_G1_OBE_EN |		 \
	 SIUL2_MSCR_MUX_MODE_ALT2)

#define SIUL2_MSCR_S32G_G1_PORT_CTRL_UART_RXD	 \
	(SIUL2_MSCR_S32_G1_SRC_100MHz |		 \
	 SIUL2_MSCR_S32_G1_IBE_EN |		 \
	 SIUL2_MSCR_MUX_MODE_ALT4)

/* UART IMCR mux modes */
#define SIUL2_IMCR_S32G_G1_UART_RXD_to_pad	(SIUL2_MSCR_MUX_MODE_ALT4)

/* S32-GEN1 uSDHC settings */
#define SIUL2_USDHC_S32_G1_PAD_CTRL_BASE \
	(SIUL2_MSCR_S32_G1_SRC_208MHz | \
	 SIUL2_MSCR_S32_G1_OBE_EN | \
	 SIUL2_MSCR_S32_G1_IBE_EN | \
	 SIUL2_MSCR_S32_G1_PUE_EN | \
	 SIUL2_MSCR_S32_G1_PUS_EN)

#define SIUL2_USDHC_S32_G1_PAD_CTRL_CMD \
	(SIUL2_USDHC_S32_G1_PAD_CTRL_BASE | \
	 SIUL2_MSCR_MUX_MODE_ALT1)

#define SIUL2_USDHC_S32_G1_PAD_CTRL_CLK \
	(SIUL2_USDHC_S32_G1_PAD_CTRL_BASE | \
	 SIUL2_MSCR_MUX_MODE_ALT1)

#define SIUL2_USDHC_S32_G1_PAD_CTRL_DATA \
	(SIUL2_USDHC_S32_G1_PAD_CTRL_BASE | \
	 SIUL2_MSCR_MUX_MODE_ALT1)

/* I2C settings */
/* S32G2XX */
#define SIUL2_MSCR_S32G_PB_00	16
#define SIUL2_MSCR_S32G_PB_01	17
#define SIUL2_MSCR_S32G_PB_03	19
#define SIUL2_MSCR_S32G_PB_04	20
#define SIUL2_MSCR_S32G_PB_05	21
#define SIUL2_MSCR_S32G_PB_06	22
#define SIUL2_MSCR_S32G_PB_07	23
#define SIUL2_MSCR_S32G_PB_13	29
#define SIUL2_MSCR_S32G_PC_01	33
#define SIUL2_MSCR_S32G_PC_02	34
#define SIUL2_PB_00_IMCR_S32G_I2C0_SDA	(565 - 512)
#define SIUL2_PB_01_IMCR_S32G_I2C0_SCLK	(566 - 512)
#define SIUL2_PB_03_IMCR_S32G_I2C1_SCLK	(717 - 512)
#define SIUL2_PB_04_IMCR_S32G_I2C1_SDA	(718 - 512)
#define SIUL2_PB_05_IMCR_S32G_I2C2_SCLK	(719 - 512)
#define SIUL2_PB_06_IMCR_S32G_I2C2_SDA	(720 - 512)
#define SIUL2_PB_07_IMCR_S32G_I2C3_SCLK	(721 - 512)
#define SIUL2_PB_13_IMCR_S32G_I2C3_SDA	(722 - 512)
#define SIUL2_PC_01_IMCR_S32G_I2C4_SDA	(724 - 512)
#define SIUL2_PC_02_IMCR_S32G_I2C4_SCLK	(723 - 512)

/* I2C0 - Serial Data Input */
#define SIUL2_MSCR_S32G_PAD_CTRL_I2C0_SDA \
	(SIUL2_MSCR_MUX_MODE_ALT1 | \
	 SIUL2_MSCR_S32_G1_OBE_EN | \
	 SIUL2_MSCR_S32_G1_IBE_EN | \
	 SIUL2_MSCR_S32_G1_ODE_EN)
#define SIUL2_IMCR_S32G_PAD_CTRL_I2C0_SDA (SIUL2_MSCR_MUX_MODE_ALT2)

/* I2C0 - Serial Clock Input */
#define SIUL2_MSCR_S32G_PAD_CTRL_I2C0_SCLK \
	(SIUL2_MSCR_MUX_MODE_ALT1 | \
	 SIUL2_MSCR_S32_G1_OBE_EN | \
	 SIUL2_MSCR_S32_G1_IBE_EN | \
	 SIUL2_MSCR_S32_G1_ODE_EN)
#define SIUL2_IMCR_S32G_PAD_CTRL_I2C0_SCLK (SIUL2_MSCR_MUX_MODE_ALT2)

/* I2C1 - Serial Data Input */
#define SIUL2_MSCR_S32G_PAD_CTRL_I2C1_SDA \
	(SIUL2_MSCR_MUX_MODE_ALT1 | \
	 SIUL2_MSCR_S32_G1_OBE_EN | \
	 SIUL2_MSCR_S32_G1_IBE_EN | \
	 SIUL2_MSCR_S32_G1_ODE_EN)
#define SIUL2_IMCR_S32G_PAD_CTRL_I2C1_SDA (SIUL2_MSCR_MUX_MODE_ALT2)

/* I2C1 - Serial Clock Input */
#define SIUL2_MSCR_S32G_PAD_CTRL_I2C1_SCLK \
	(SIUL2_MSCR_MUX_MODE_ALT1 | \
	 SIUL2_MSCR_S32_G1_OBE_EN | \
	 SIUL2_MSCR_S32_G1_IBE_EN | \
	 SIUL2_MSCR_S32_G1_ODE_EN)
#define SIUL2_IMCR_S32G_PAD_CTRL_I2C1_SCLK (SIUL2_MSCR_MUX_MODE_ALT2)

/* I2C2 - Serial Data Input */
#define SIUL2_MSCR_S32G_PAD_CTRL_I2C2_SDA \
	(SIUL2_MSCR_MUX_MODE_ALT1 | \
	 SIUL2_MSCR_S32_G1_OBE_EN | \
	 SIUL2_MSCR_S32_G1_IBE_EN | \
	 SIUL2_MSCR_S32_G1_ODE_EN)
#define SIUL2_IMCR_S32G_PAD_CTRL_I2C2_SDA (SIUL2_MSCR_MUX_MODE_ALT2)

/* I2C2 - Serial Clock Input */
#define SIUL2_MSCR_S32G_PAD_CTRL_I2C2_SCLK \
	(SIUL2_MSCR_MUX_MODE_ALT1 | \
	 SIUL2_MSCR_S32_G1_OBE_EN | \
	 SIUL2_MSCR_S32_G1_IBE_EN | \
	 SIUL2_MSCR_S32_G1_ODE_EN)
#define SIUL2_IMCR_S32G_PAD_CTRL_I2C2_SCLK (SIUL2_MSCR_MUX_MODE_ALT2)

/* I2C3 - Serial Data Input */
#define SIUL2_MSCR_S32G_PAD_CTRL_I2C3_SDA \
	(SIUL2_MSCR_MUX_MODE_ALT2 | \
	 SIUL2_MSCR_S32_G1_OBE_EN | \
	 SIUL2_MSCR_S32_G1_IBE_EN | \
	 SIUL2_MSCR_S32_G1_ODE_EN)
#define SIUL2_IMCR_S32G_PAD_CTRL_I2C3_SDA (SIUL2_MSCR_MUX_MODE_ALT4)

/* I2C3 - Serial Clock Input */
#define SIUL2_MSCR_S32G_PAD_CTRL_I2C3_SCLK \
	(SIUL2_MSCR_MUX_MODE_ALT1 | \
	 SIUL2_MSCR_S32_G1_OBE_EN | \
	 SIUL2_MSCR_S32_G1_IBE_EN | \
	 SIUL2_MSCR_S32_G1_ODE_EN)
#define SIUL2_IMCR_S32G_PAD_CTRL_I2C3_SCLK (SIUL2_MSCR_MUX_MODE_ALT2)

/* I2C4 - Serial Data Input */
#define SIUL2_MSCR_S32G_PAD_CTRL_I2C4_SDA \
	(SIUL2_MSCR_MUX_MODE_ALT1 | \
	 SIUL2_MSCR_S32_G1_OBE_EN | \
	 SIUL2_MSCR_S32_G1_IBE_EN | \
	 SIUL2_MSCR_S32_G1_ODE_EN)
#define SIUL2_IMCR_S32G_PAD_CTRL_I2C4_SDA (SIUL2_MSCR_MUX_MODE_ALT3)

/* I2C4 - Serial Clock Input */
#define SIUL2_MSCR_S32G_PAD_CTRL_I2C4_SCLK \
	(SIUL2_MSCR_MUX_MODE_ALT2 | \
	 SIUL2_MSCR_S32_G1_OBE_EN | \
	 SIUL2_MSCR_S32_G1_IBE_EN | \
	 SIUL2_MSCR_S32_G1_ODE_EN)
#define SIUL2_IMCR_S32G_PAD_CTRL_I2C4_SCLK (SIUL2_MSCR_MUX_MODE_ALT3)

/* S32V344 */
#define SIUL2_MSCR_S32V_PB_00	16
#define SIUL2_MSCR_S32V_PB_01	17
#define SIUL2_MSCR_S32V_PA_06	6
#define SIUL2_MSCR_S32V_PA_07	7
#define SIUL2_MSCR_S32V_PA_14	14
#define SIUL2_MSCR_S32V_PA_15	15
#define SIUL2_MSCR_S32V_PB_06	22
#define SIUL2_MSCR_S32V_PB_07	23
#define SIUL2_MSCR_S32V_PD_11	59
#define SIUL2_MSCR_S32V_PC_13	45
#define SIUL2_PB_00_IMCR_S32V_I2C0_SDA	(565 - 512)
#define SIUL2_PB_01_IMCR_S32V_I2C0_SCLK	(566 - 512)
#define SIUL2_PA_06_IMCR_S32V_I2C1_SDA	(601 - 512)
#define SIUL2_PA_07_IMCR_S32V_I2C1_SCLK	(600 - 512)
#define SIUL2_PA_14_IMCR_S32V_I2C2_SDA	(603 - 512)
#define SIUL2_PA_15_IMCR_S32V_I2C2_SCLK	(602 - 512)
#define SIUL2_PB_06_IMCR_S32V_I2C3_SDA	(605 - 512)
#define SIUL2_PB_07_IMCR_S32V_I2C3_SCLK	(604 - 512)
#define SIUL2_PD_11_IMCR_S32V_I2C4_SDA	(606 - 512)
#define SIUL2_PC_13_IMCR_S32V_I2C4_SCLK	(607 - 512)

/* I2C0 - Serial Data Input */
#define SIUL2_MSCR_S32V_PAD_CTRL_I2C0_SDA \
	(SIUL2_MSCR_MUX_MODE_ALT1 | \
	 SIUL2_MSCR_S32_G1_OBE_EN | \
	 SIUL2_MSCR_S32_G1_IBE_EN | \
	 SIUL2_MSCR_S32_G1_ODE_EN)
#define SIUL2_IMCR_S32V_PAD_CTRL_I2C0_SDA (SIUL2_MSCR_MUX_MODE_ALT2)

/* I2C0 - Serial Clock Input */
#define SIUL2_MSCR_S32V_PAD_CTRL_I2C0_SCLK \
	(SIUL2_MSCR_MUX_MODE_ALT1 | \
	 SIUL2_MSCR_S32_G1_OBE_EN | \
	 SIUL2_MSCR_S32_G1_IBE_EN | \
	 SIUL2_MSCR_S32_G1_ODE_EN)
#define SIUL2_IMCR_S32V_PAD_CTRL_I2C0_SCLK (SIUL2_MSCR_MUX_MODE_ALT2)

/* I2C1 - Serial Data Input */
#define SIUL2_MSCR_S32V_PAD_CTRL_I2C1_SDA \
	(SIUL2_MSCR_MUX_MODE_ALT2 | \
	 SIUL2_MSCR_S32_G1_OBE_EN | \
	 SIUL2_MSCR_S32_G1_IBE_EN | \
	 SIUL2_MSCR_S32_G1_ODE_EN)
#define SIUL2_IMCR_S32V_PAD_CTRL_I2C1_SDA (SIUL2_MSCR_MUX_MODE_ALT3)

/* I2C1 - Serial Clock Input */
#define SIUL2_MSCR_S32V_PAD_CTRL_I2C1_SCLK \
	(SIUL2_MSCR_MUX_MODE_ALT2 | \
	 SIUL2_MSCR_S32_G1_OBE_EN | \
	 SIUL2_MSCR_S32_G1_IBE_EN | \
	 SIUL2_MSCR_S32_G1_ODE_EN)
#define SIUL2_IMCR_S32V_PAD_CTRL_I2C1_SCLK (SIUL2_MSCR_MUX_MODE_ALT3)

/* I2C2 - Serial Data Input */
#define SIUL2_MSCR_S32V_PAD_CTRL_I2C2_SDA \
	(SIUL2_MSCR_MUX_MODE_ALT1 | \
	 SIUL2_MSCR_S32_G1_OBE_EN | \
	 SIUL2_MSCR_S32_G1_IBE_EN | \
	 SIUL2_MSCR_S32_G1_ODE_EN)
#define SIUL2_IMCR_S32V_PAD_CTRL_I2C2_SDA (SIUL2_MSCR_MUX_MODE_ALT2)

/* I2C2 - Serial Clock Input */
#define SIUL2_MSCR_S32V_PAD_CTRL_I2C2_SCLK \
	(SIUL2_MSCR_MUX_MODE_ALT1 | \
	 SIUL2_MSCR_S32_G1_OBE_EN | \
	 SIUL2_MSCR_S32_G1_IBE_EN | \
	 SIUL2_MSCR_S32_G1_ODE_EN)
#define SIUL2_IMCR_S32V_PAD_CTRL_I2C2_SCLK (SIUL2_MSCR_MUX_MODE_ALT2)

/* I2C3 - Serial Data Input */
#define SIUL2_MSCR_S32V_PAD_CTRL_I2C3_SDA \
	(SIUL2_MSCR_MUX_MODE_ALT1 | \
	 SIUL2_MSCR_S32_G1_OBE_EN | \
	 SIUL2_MSCR_S32_G1_IBE_EN | \
	 SIUL2_MSCR_S32_G1_ODE_EN)
#define SIUL2_IMCR_S32V_PAD_CTRL_I2C3_SDA (SIUL2_MSCR_MUX_MODE_ALT2)

/* I2C3 - Serial Clock Input */
#define SIUL2_MSCR_S32V_PAD_CTRL_I2C3_SCLK \
	(SIUL2_MSCR_MUX_MODE_ALT1 | \
	 SIUL2_MSCR_S32_G1_OBE_EN | \
	 SIUL2_MSCR_S32_G1_IBE_EN | \
	 SIUL2_MSCR_S32_G1_ODE_EN)
#define SIUL2_IMCR_S32V_PAD_CTRL_I2C3_SCLK (SIUL2_MSCR_MUX_MODE_ALT2)

/* I2C4 - Serial Data Input */
#define SIUL2_MSCR_S32V_PAD_CTRL_I2C4_SDA \
	(SIUL2_MSCR_MUX_MODE_ALT2 | \
	 SIUL2_MSCR_S32_G1_OBE_EN | \
	 SIUL2_MSCR_S32_G1_IBE_EN | \
	 SIUL2_MSCR_S32_G1_ODE_EN)
#define SIUL2_IMCR_S32V_PAD_CTRL_I2C4_SDA (SIUL2_MSCR_MUX_MODE_ALT2)

/* I2C4 - Serial Clock Input */
#define SIUL2_MSCR_S32V_PAD_CTRL_I2C4_SCLK \
	(SIUL2_MSCR_MUX_MODE_ALT2 | \
	 SIUL2_MSCR_S32_G1_OBE_EN | \
	 SIUL2_MSCR_S32_G1_IBE_EN | \
	 SIUL2_MSCR_S32_G1_ODE_EN)
#define SIUL2_IMCR_S32V_PAD_CTRL_I2C4_SCLK (SIUL2_MSCR_MUX_MODE_ALT2)

/* S32R45X */
#define SIUL2_MSCR_S32R_PB_00	16
#define SIUL2_MSCR_S32R_PB_01	17
#define SIUL2_MSCR_S32R_PA_15	15
#define SIUL2_MSCR_S32R_PA_14	14
#define SIUL2_PB_00_IMCR_S32R_I2C0_SDA	(565 - 512)
#define SIUL2_PB_01_IMCR_S32R_I2C0_SCLK	(566 - 512)
#define SIUL2_PA_15_IMCR_S32R_I2C1_SDA	(616 - 512)
#define SIUL2_PA_14_IMCR_S32R_I2C1_SCLK	(615 - 512)

/* I2C0 - Serial Data Input */
#define SIUL2_MSCR_S32R_PAD_CTRL_I2C0_SDA \
	(SIUL2_MSCR_MUX_MODE_ALT1 | \
	 SIUL2_MSCR_S32_G1_OBE_EN | \
	 SIUL2_MSCR_S32_G1_IBE_EN | \
	 SIUL2_MSCR_S32_G1_ODE_EN)
#define SIUL2_IMCR_S32R_PAD_CTRL_I2C0_SDA (SIUL2_MSCR_MUX_MODE_ALT2)

/* I2C0 - Serial Clock Input */
#define SIUL2_MSCR_S32R_PAD_CTRL_I2C0_SCLK \
	(SIUL2_MSCR_MUX_MODE_ALT1 | \
	 SIUL2_MSCR_S32_G1_OBE_EN | \
	 SIUL2_MSCR_S32_G1_IBE_EN | \
	 SIUL2_MSCR_S32_G1_ODE_EN)
#define SIUL2_IMCR_S32R_PAD_CTRL_I2C0_SCLK (SIUL2_MSCR_MUX_MODE_ALT2)

/* I2C1 - Serial Data Input */
#define SIUL2_MSCR_S32R_PAD_CTRL_I2C1_SDA \
	(SIUL2_MSCR_MUX_MODE_ALT3 | \
	 SIUL2_MSCR_S32_G1_OBE_EN | \
	 SIUL2_MSCR_S32_G1_IBE_EN | \
	 SIUL2_MSCR_S32_G1_ODE_EN)
#define SIUL2_IMCR_S32R_PAD_CTRL_I2C1_SDA (SIUL2_MSCR_MUX_MODE_ALT2)

/* I2C1 - Serial Clock Input */
#define SIUL2_MSCR_S32R_PAD_CTRL_I2C1_SCLK \
	(SIUL2_MSCR_MUX_MODE_ALT4 | \
	 SIUL2_MSCR_S32_G1_OBE_EN | \
	 SIUL2_MSCR_S32_G1_IBE_EN | \
	 SIUL2_MSCR_S32_G1_ODE_EN)
#define SIUL2_IMCR_S32R_PAD_CTRL_I2C1_SCLK (SIUL2_MSCR_MUX_MODE_ALT2)

/* S32G-GEN1 ENET settings */
/* GMAC0 MDC*/
#define SIUL2_MSCR_S32_G1_PD12		60
/* GMAC0 MDIO*/
#define SIUL2_MSCR_S32_G1_PD13		61
#define SIUL2_MSCR_S32_G1_PD13_IN	527

/* GMAC0 TX CLK*/
#define SIUL2_MSCR_S32_G1_PE2		66
#define SIUL2_MSCR_S32_G1_PE2_IN	538

/* GMAC0 TX EN*/
#define SIUL2_MSCR_S32_G1_PE3		67

/* GMAC0 TX DATA0-3*/
#define SIUL2_MSCR_S32_G1_PE4		68
#define SIUL2_MSCR_S32_G1_PE5		69
#define SIUL2_MSCR_S32_G1_PE6		70
#define SIUL2_MSCR_S32_G1_PE7		71

/* GMAC0 RX CLK*/
#define SIUL2_MSCR_S32_G1_PE8		72
#define SIUL2_MSCR_S32_G1_PE8_IN	529

/* GMAC0 RX ER*/
#define SIUL2_MSCR_S32_G1_PE9		73
#define SIUL2_MSCR_S32_G1_PE9_IN	530

/* GMAC0 RX DATA0-3*/
#define SIUL2_MSCR_S32_G1_PE10		74
#define SIUL2_MSCR_S32_G1_PE10_IN	531

#define SIUL2_MSCR_S32_G1_PE11		75
#define SIUL2_MSCR_S32_G1_PE11_IN	532

#define SIUL2_MSCR_S32_G1_PE12		76
#define SIUL2_MSCR_S32_G1_PE12_IN	533

#define SIUL2_MSCR_S32_G1_PE13		77
#define SIUL2_MSCR_S32_G1_PE13_IN	534

#define SIUL2_MSCR_S32_G1_ENET_MDC	\
	(SIUL2_MSCR_S32_G1_SRC_208MHz | \
	 SIUL2_MSCR_S32_G1_OBE_EN | \
	 SIUL2_MSCR_MUX_MODE_ALT1)

#define SIUL2_MSCR_S32_G1_ENET_MDIO	\
	(SIUL2_MSCR_S32_G1_SRC_208MHz | \
	 SIUL2_MSCR_S32_G1_OBE_EN | \
	 SIUL2_MSCR_S32_G1_IBE_EN | \
	 SIUL2_MSCR_MUX_MODE_ALT1)

#define SIUL2_MSCR_S32_G1_ENET_MDIO_IN		SIUL2_MSCR_MUX_MODE_ALT2

#define SIUL2_MSCR_S32_G1_ENET_TX_CLK \
	(SIUL2_MSCR_S32_G1_SRC_50MHz | \
	 SIUL2_MSCR_S32_G1_PUS_EN | \
	 SIUL2_MSCR_S32_G1_OBE_EN | \
	 SIUL2_MSCR_MUX_MODE_ALT1)

#define SIUL2_MSCR_S32_G1_ENET_TX_CLK_IN	SIUL2_MSCR_MUX_MODE_ALT2

#define SIUL2_MSCR_S32_G1_ENET_RX_CLK	\
	 (SIUL2_MSCR_S32_G1_IBE_EN)

#define SIUL2_MSCR_S32_G1_ENET_RX_CLK_IN	SIUL2_MSCR_MUX_MODE_ALT2

#define SIUL2_MSCR_S32_G1_ENET_RX_D0	\
	 (SIUL2_MSCR_S32_G1_IBE_EN)

#define SIUL2_MSCR_S32_G1_ENET_RX_D0_IN		SIUL2_MSCR_MUX_MODE_ALT2

#define SIUL2_MSCR_S32_G1_ENET_RX_D1	\
	 (SIUL2_MSCR_S32_G1_IBE_EN)

#define SIUL2_MSCR_S32_G1_ENET_RX_D1_IN		SIUL2_MSCR_MUX_MODE_ALT2

#define SIUL2_MSCR_S32_G1_ENET_RX_D2	\
	 (SIUL2_MSCR_S32_G1_IBE_EN)

#define SIUL2_MSCR_S32_G1_ENET_RX_D2_IN		SIUL2_MSCR_MUX_MODE_ALT2

#define SIUL2_MSCR_S32_G1_ENET_RX_D3	\
	 (SIUL2_MSCR_S32_G1_IBE_EN)

#define SIUL2_MSCR_S32_G1_ENET_RX_D3_IN		SIUL2_MSCR_MUX_MODE_ALT2

#define SIUL2_MSCR_S32_G1_ENET_RX_DV	\
	 (SIUL2_MSCR_S32_G1_IBE_EN)

#define SIUL2_MSCR_S32_G1_ENET_RX_DV_IN		SIUL2_MSCR_MUX_MODE_ALT2

#define SIUL2_MSCR_S32_G1_ENET_RX_ER	\
	 (SIUL2_MSCR_S32_G1_IBE_EN)

#define SIUL2_MSCR_S32_G1_ENET_RX_ER_IN		SIUL2_MSCR_MUX_MODE_ALT2

#define SIUL2_MSCR_S32_G1_ENET_TX_D0	\
	(SIUL2_MSCR_S32_G1_SRC_208MHz | \
	 SIUL2_MSCR_S32_G1_OBE_EN | \
	 SIUL2_MSCR_MUX_MODE_ALT1)

#define SIUL2_MSCR_S32_G1_ENET_TX_D1	\
	(SIUL2_MSCR_S32_G1_SRC_208MHz | \
	 SIUL2_MSCR_S32_G1_OBE_EN | \
	 SIUL2_MSCR_MUX_MODE_ALT1)

#define SIUL2_MSCR_S32_G1_ENET_TX_D2	\
	(SIUL2_MSCR_S32_G1_SRC_208MHz | \
	 SIUL2_MSCR_S32_G1_OBE_EN | \
	 SIUL2_MSCR_MUX_MODE_ALT1)

#define SIUL2_MSCR_S32_G1_ENET_TX_D3	\
	(SIUL2_MSCR_S32_G1_SRC_208MHz | \
	 SIUL2_MSCR_S32_G1_OBE_EN | \
	 SIUL2_MSCR_MUX_MODE_ALT1)

#define SIUL2_MSCR_S32_G1_ENET_TX_EN	\
	(SIUL2_MSCR_S32_G1_SRC_208MHz | \
	 SIUL2_MSCR_S32_G1_OBE_EN | \
	 SIUL2_MSCR_MUX_MODE_ALT1)

#define SIUL2_MSCR_S32_G1_ENET_RMII_CLK_REF_IP	\
	 (SIUL2_MSCR_S32_G1_IBE_EN)

/* QSPI configuration  */
#define SIUL2_MSCR_S32_G1_QSPI_BASE \
	(SIUL2_MSCR_S32_G1_SRC_208MHz | \
	 SIUL2_MSCR_S32_G1_OBE_EN | \
	 SIUL2_MSCR_S32_G1_IBE_EN)

#define SIUL2_MSCR_S32_G1_QSPI_CLK_BASE	\
	(SIUL2_MSCR_S32_G1_SRC_208MHz | \
	 SIUL2_MSCR_S32_G1_OBE_EN)

#define SIUL2_MSCR_S32_G1_QSPI_CK2_MUX		SIUL2_MSCR_MUX_MODE_ALT1
#define SIUL2_MSCR_S32_G1_QSPI_A_SCK_MUX	SIUL2_MSCR_MUX_MODE_ALT1
#define SIUL2_MSCR_S32_G1_QSPI_B_SCK_MUX	SIUL2_MSCR_MUX_MODE_ALT2
#define SIUL2_MSCR_S32_G1_QSPI_A_CS0_MUX	SIUL2_MSCR_MUX_MODE_ALT1
#define SIUL2_MSCR_S32_G1_QSPI_B_CS0_MUX	SIUL2_MSCR_MUX_MODE_ALT2
#define SIUL2_MSCR_S32_G1_QSPI_A_CS1_MUX	SIUL2_MSCR_MUX_MODE_ALT1
#define SIUL2_MSCR_S32_G1_QSPI_B_CS1_MUX	SIUL2_MSCR_MUX_MODE_ALT2
#define SIUL2_IMCR_S32_G1_QSPI_A_DATA_MUX	SIUL2_MSCR_MUX_MODE_ALT2
#define SIUL2_IMCR_S32_G1_QSPI_B_DATA_MUX	SIUL2_MSCR_MUX_MODE_ALT2

#define SIUL2_MSCR_S32_G1_QSPI_A_DQS \
	(SIUL2_MSCR_S32_G1_SRC_208MHz | \
	 SIUL2_MSCR_S32_G1_IBE_EN | \
	 SIUL2_MSCR_S32_G1_OBE_EN | \
	 SIUL2_MSCR_S32_G1_PUE_EN)

#define SIUL2_MSCR_S32_G1_QSPI_A_DATA0_7 \
	(SIUL2_MSCR_S32_G1_QSPI_BASE | \
	 SIUL2_MSCR_MUX_MODE_ALT1)

#define SIUL2_MSCR_S32_G1_QSPI_B_DATA0_7 \
	(SIUL2_MSCR_S32_G1_QSPI_BASE | \
	 SIUL2_MSCR_MUX_MODE_ALT2)

/* QSPI configuration */
/* Note as-is DQS not enabled OR PAD_CTL_QSPI_A_DQS to enable */
#define SIUL2_MSCR_S32_G1_PF13__QSPI_A_DQS        548
#define SIUL2_MSCR_S32_G1_PD4__QSPI_B_DQS         558

#define SIUL2_MSCR_S32_G1_PF5__QSPI_A_DATA0_IN    540
#define SIUL2_MSCR_S32_G1_PF5__QSPI_A_DATA0_OUT   85

#define SIUL2_MSCR_S32_G1_PF6__QSPI_A_DATA1_IN    541
#define SIUL2_MSCR_S32_G1_PF6__QSPI_A_DATA1_OUT   86

#define SIUL2_MSCR_S32_G1_PF7__QSPI_A_DATA2_IN    542
#define SIUL2_MSCR_S32_G1_PF7__QSPI_A_DATA2_OUT   87

#define SIUL2_MSCR_S32_G1_PF8__QSPI_A_DATA3_IN    543
#define SIUL2_MSCR_S32_G1_PF8__QSPI_A_DATA3_OUT   88

#define SIUL2_MSCR_S32_G1_PF9__QSPI_A_DATA4_IN    544
#define SIUL2_MSCR_S32_G1_PF9__QSPI_A_DATA4_OUT   89

#define SIUL2_MSCR_S32_G1_PF10__QSPI_A_DATA5_IN   545
#define SIUL2_MSCR_S32_G1_PF10__QSPI_A_DATA5_OUT  90

#define SIUL2_MSCR_S32_G1_PF11__QSPI_A_DATA6_IN   546
#define SIUL2_MSCR_S32_G1_PF11__QSPI_A_DATA6_OUT  91

#define SIUL2_MSCR_S32_G1_PF12__QSPI_A_DATA7_IN   547
#define SIUL2_MSCR_S32_G1_PF12__QSPI_A_DATA7_OUT  92

#define SIUL2_MSCR_S32_G1_PC14__QSPI_B_DATA0_IN   552
#define SIUL2_MSCR_S32_G1_PC14__QSPI_B_DATA0_OUT  46

#define SIUL2_MSCR_S32_G1_PD3__QSPI_B_DATA1_IN    554
#define SIUL2_MSCR_S32_G1_PD3__QSPI_B_DATA1_OUT   51

#define SIUL2_MSCR_S32_G1_PD9__QSPI_B_DATA2_IN    551
#define SIUL2_MSCR_S32_G1_PD9__QSPI_B_DATA2_OUT   57

#define SIUL2_MSCR_S32_G1_PC15__QSPI_B_DATA3_IN   553
#define SIUL2_MSCR_S32_G1_PC15__QSPI_B_DATA3_OUT  47

#define SIUL2_MSCR_S32_G1_PD2__QSPI_B_DATA4_IN    557
#define SIUL2_MSCR_S32_G1_PD2__QSPI_B_DATA4_OUT   50

#define SIUL2_MSCR_S32_G1_PD8__QSPI_B_DATA5_IN    550
#define SIUL2_MSCR_S32_G1_PD8__QSPI_B_DATA5_OUT   56

#define SIUL2_MSCR_S32_G1_PD10__QSPI_B_DATA6_IN   556
#define SIUL2_MSCR_S32_G1_PD10__QSPI_B_DATA6_OUT  58

#define SIUL2_MSCR_S32_G1_PD5__QSPI_B_DATA7_IN    555
#define SIUL2_MSCR_S32_G1_PD5__QSPI_B_DATA7_OUT   53

#define SIUL2_MSCR_S32_G1_PG5__QSPI_A_CS1         101
#define SIUL2_MSCR_S32_G1_PD1__QSPI_B_CS1         49

#define SIUL2_MSCR_S32_G1_PG4__QSPI_A_CS0         100
#define SIUL2_MSCR_S32_G1_PG0__QSPI_A_SCK         96

#define SIUL2_MSCR_S32_G1_PD0__QSPI_B_CS0         48
#define SIUL2_MSCR_S32_G1_PD6__QSPI_B_SCK         54

#define SIUL2_MSCR_S32_G1_PG2__QSPI_CK2           98

/* DSPI Configuration */
/* S32G2XX */

#define SIUL2_MSCR_S32G_PA_13	13
#define SIUL2_MSCR_S32G_PA_14	14
#define SIUL2_MSCR_S32G_PA_15	15
#define SIUL2_MSCR_S32G_PB_00	16

#define SIUL2_MSCR_S32_G1_PAD_CTL_SPI_CSx \
	(SIUL2_MSCR_S32_G1_OBE_EN | SIUL2_MSCR_S32_G1_PUE_EN | \
	 SIUL2_MSCR_S32_G1_PUS)

#define SUIL2_MSCR_S32G_PAD_CTL_SPI0_CS0 \
	(SIUL2_MSCR_S32_G1_PAD_CTL_SPI_CSx | \
	 SIUL2_MSCR_MUX_MODE_ALT2)

#define SIUL2_MSCR_S32G_PAD_CTL_SPI0_SCK	(SIUL2_MSCR_S32_G1_OBE_EN | \
						 SIUL2_MSCR_MUX_MODE_ALT1)

#define SIUL2_MSCR_S32G_PAD_CTL_SPI0_SOUT	(SIUL2_MSCR_S32_G1_OBE_EN | \
						 SIUL2_MSCR_MUX_MODE_ALT1)

#define SIUL2_MSCR_S32G_PAD_CTL_SPI0_SIN	(SIUL2_MSCR_S32_G1_IBE_EN | \
						 SIUL2_MSCR_S32_G1_PUE_EN | \
						 SIUL2_MSCR_S32_G1_PUS)

#define SIUL2_IMCR_S32G_PAD_CTL_SPI0_SIN	(SIUL2_MSCR_MUX_MODE_ALT2)
#define SIUL2_PA_14_IMCR_S32G_SPI0_SIN    (982 - 512)

/* S32V344 */
#define SIUL2_MSCR_S32V_PJ_06	134
#define SIUL2_MSCR_S32V_PJ_07	135
#define SIUL2_MSCR_S32V_PJ_08	136
#define SIUL2_MSCR_S32V_PJ_09	137
#define SIUL2_MSCR_S32V_PJ_10	138

#define SUIL2_MSCR_S32V_PAD_CTL_SPI0_CS0 \
	(SIUL2_MSCR_S32_G1_PAD_CTL_SPI_CSx | \
	 SIUL2_MSCR_MUX_MODE_ALT1)

#define SUIL2_MSCR_S32V_PAD_CTL_SPI0_CS1 \
	(SIUL2_MSCR_S32_G1_PAD_CTL_SPI_CSx | \
	 SIUL2_MSCR_MUX_MODE_ALT1)

#define SIUL2_MSCR_S32V_PAD_CTL_SPI0_SCK	(SIUL2_MSCR_S32_G1_OBE_EN | \
						 SIUL2_MSCR_MUX_MODE_ALT1)

#define SIUL2_MSCR_S32V_PAD_CTL_SPI0_SOUT	(SIUL2_MSCR_S32_G1_OBE_EN | \
						 SIUL2_MSCR_MUX_MODE_ALT1)

#define SIUL2_MSCR_S32V_PAD_CTL_SPI0_SIN	(SIUL2_MSCR_S32_G1_IBE_EN | \
						 SIUL2_MSCR_S32_G1_PUE_EN | \
						 SIUL2_MSCR_S32_G1_PUS)

#define SIUL2_IMCR_S32V_PAD_CTL_SPI0_SIN	(SIUL2_MSCR_MUX_MODE_ALT2)
#define SIUL2_PJ_07_IMCR_S32V_SPI0_SIN    (562 - 512)

/* S32R45X */
#define SIUL2_MSCR_S32R_PA_9	9
#define SIUL2_MSCR_S32R_PA_10	10
#define SIUL2_MSCR_S32R_PJ_4	132
#define SIUL2_MSCR_S32R_PJ_5	133

#define SUIL2_MSCR_S32V_PAD_CTL_SPI5_CS0 \
	(SIUL2_MSCR_S32_G1_PAD_CTL_SPI_CSx | \
	 SIUL2_MSCR_MUX_MODE_ALT2)

#define SIUL2_MSCR_S32R_PAD_CTL_SPI5_SCK	(SIUL2_MSCR_S32_G1_OBE_EN | \
						 SIUL2_MSCR_MUX_MODE_ALT2)

#define SIUL2_MSCR_S32R_PAD_CTL_SPI5_SOUT	(SIUL2_MSCR_S32_G1_OBE_EN | \
						 SIUL2_MSCR_MUX_MODE_ALT4)

#define SIUL2_MSCR_S32R_PAD_CTL_SPI5_SIN	(SIUL2_MSCR_S32_G1_IBE_EN | \
						 SIUL2_MSCR_S32_G1_PUE_EN | \
						 SIUL2_MSCR_S32_G1_PUS)

#define SIUL2_IMCR_S32R_PAD_CTL_SPI5_SIN	(SIUL2_MSCR_MUX_MODE_ALT4)
#define SIUL2_PJ_4_IMCR_S32R_SPI5_SIN    (750 - 512)

#ifdef CONFIG_FSL_DCU_FB

/* DCU Settings */

#define SIUL2_MSCR_S32V_PH0	105
#define SIUL2_MSCR_S32V_PH1	106
#define SIUL2_MSCR_S32V_PH2	107
#define SIUL2_MSCR_S32V_PH3	108
#define SIUL2_MSCR_S32V_PH4	109
#define SIUL2_MSCR_S32V_PH5	110
#define SIUL2_MSCR_S32V_PH6	111
#define SIUL2_MSCR_S32V_PH7	112
#define SIUL2_MSCR_S32V_PH8	113
#define SIUL2_MSCR_S32V_PH9	114
#define SIUL2_MSCR_S32V_PH10	115
#define SIUL2_MSCR_S32V_PH11	116
#define SIUL2_MSCR_S32V_PH12	117
#define SIUL2_MSCR_S32V_PH13	118
#define SIUL2_MSCR_S32V_PH14	119
#define SIUL2_MSCR_S32V_PH15	120
#define SIUL2_MSCR_S32V_PI0	121
#define SIUL2_MSCR_S32V_PI1	122
#define SIUL2_MSCR_S32V_PI2	123
#define SIUL2_MSCR_S32V_PI3	124
#define SIUL2_MSCR_S32V_PI4	125
#define SIUL2_MSCR_S32V_PI5	126
#define SIUL2_MSCR_S32V_PI6	127
#define SIUL2_MSCR_S32V_PI7	128
#define SIUL2_MSCR_S32V_PI8	129
#define SIUL2_MSCR_S32V_PI9	130
#define SIUL2_MSCR_S32V_PI10	131
#define SIUL2_MSCR_S32V_PI11	132
#define SIUL2_MSCR_S32V_PI12	133

#define SIUL2_MSCR_S32V_DCU_CFG \
	(SIUL2_MSCR_S32_G1_SRC_208MHz | \
	 SIUL2_MSCR_S32_G1_OBE_EN | \
	 SIUL2_MSCR_S32_G1_IBE_EN | \
	 SIUL2_MSCR_MUX_MODE_ALT1)

#endif /* CONFIG_FSL_DCU_FB */

#endif /*__ARCH_ARM_MACH_S32G1_SIUL_H__ */
